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ATmega128
? OC1B, Bit 6
OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the
Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one))
to serve this function. The OC1B pin is also the output pin for the P W M mode timer function.
? OC1A, Bit 5
OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one))
to serve this function. The OC1A pin is also the output pin for the P W M mode timer function.
? OC0, Bit 4
OC0, Output Compare Match output: The PB4 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to
serve this function. The OC0 pin is also the output pin for the P W M mode timer function.
? MISO – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. W hen the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB3. W hen the SPI is
enabled as a slave, the data direction of this pin is controlled by DDB3. W hen the pin is forced to
be an input, the pull-up can still be controlled by the PORTB3 bit.
? MOSI – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. W hen the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB2. W hen the SPI is
enabled as a master, the data direction of this pin is controlled by DDB2. W hen the pin is forced
to be an input, the pull-up can still be controlled by the PORTB2 bit.
? SCK – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. W hen the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. W hen the SPI is
enabled as a master, the data direction of this pin is controlled by DDB1. W hen the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
? SS – Port B, Bit 0
SS: Slave Port Select input. W hen the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. W hen the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
W hen the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 31 and Table 32 relate the alternate functions of Port B to the overriding signals shown in
Figure 33 on page 70 . SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal,
while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
74
2467X–AVR–06/11
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